ANALYSIS OF 6T SRAM CELL USING FINFET AT NANOMETER REGIME

Authors

  • Ms. M. S. Mhaske Department Of Electronics Engineering / PREC, Loni
  • Mr. P. B. Vikhe Department. Of Computer Engineering / PREC, Loni
  • Prof. S. A. Shaikh Department Of Electronics & Telecommunication Engineering / PREC, Loni

Keywords:

Cell Ratio (CR),, Pull up Ratio(PR), Silicon on Insulator(SOI),

Abstract

The fast growing technology developments in the metal oxide semiconductor area have scaled down CMOS to the sub 32nm regime. According to International Technology Roadmap For Semiconductors projection by the 2020, the printed gate lengths will scale down to 12nm. Instead of SiO2 with AL metal gate Hafnium Oxide [HFO2] can be used as a High k material. To increased chip functionality demand, SRAM area have mostly exceed overall chip area. The stability of SRAM cell depends on variation in Process, Temperature and Voltage. This paper will discuss the detail about 6T SRAM stability in standby, read and write mode design considering Double Gate MOSFET at 32nm technology node.

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Published

2021-03-27

Issue

2015: ICITDCEME

Section

Articles

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