DESIGN LBIST USING STUMPS ARCHITECTURE

Authors

  • Shubham P. Suke Electronics and Telecommunication, Sinhgad College of Engineering, Pune, India.
  • Prof. Pushpa. M. Bangare Electronics and Telecommunication, Sinhgad College of Engineering, Pune, India.

Keywords:

BIST,, LBIST,, LFSR,, MISR,

Abstract

The rapidly increasing complexity of IC designs makes testing of VLSI chips more difficult due to occurrence of faults in the VLSI chips. This lead to development of testing technology called Logic Built in Self-Test (L-BIST). Design of reconfigurable Linear Feedback Shift Register (LFSR) for VLSI IC testing is implemented in LBIST. Reconfigurable LFSR can be used in logic BIST for improvement in Fault coverage of IC testing.Self-Test Using MISR/Parallel SRSG (STUMPS) architecture is used in logic BIST.The main intention of this paper work is to understand the performance and design of LBIST using STUMPS for VLSI IC testing and analyzing speed, fault coverage and power.

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Published

2021-03-27

Issue

2019: ICSD

Section

Articles

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How to Cite

Shubham P. Suke, & Prof. Pushpa. M. Bangare. (2021). DESIGN LBIST USING STUMPS ARCHITECTURE . International Journal of Innovations in Engineering Research and Technology, 1-3. https://repo.ijiert.org/index.php/ijiert/article/view/2051