AN EFFICIENT IMPLEMENTATION OF POLAR ENCODER

Abstract

Proposed for promisinghigh speed 5G system using radix 2r based polar encoder in VLSI architecture, including single radix and reconfigurable multi-radix modes. The polar codes are considered as one of the most favourable error correcting code because of its channel achieving property. This property helps to handle the long length codes. When code length is small, fully parallel encoder implementation is easy. But when the code length increases, the hardware implementation becomes more complex. To overcomethe disadvantage of fully parallel encoder, partially parallel encoder is designed. The newly designed encoder handles long polar codes with less hardware complexity. The main advantage of proposed encoder architecture is less hardware complexity, reduceddelay and detection of error and power consumption. Partially encoder architecture is designed and synthesized by using Xilinx 12.2. The results are simulated by using ModelSim 10.4a simulating tool.