OVERVIEW OF POWER OPTIMIZATION TECHNIQUES IN WIRELESS PERSONAL AREA NETWORK

Authors

  • RAMESH Y. MALI Shri Jagdishprasad Jhabarmal Tibrewala University , Vidyanagari, Dist. Jhunjhunu, Rajasthan (India)–
  • DR. PRADEEP B. MANE Principal,A.I.S.S.M.S.,Institute of Technology,Pune, Maharashtra

Keywords:

CMOS, integrated circuit (IC),, low power,, RF transceiver,

Abstract

A low power CMOS based RF transceiver architectures are proposed with the gigahertz frequency for the applications in the field of the industrial, scientific and medical .The integrated circuit (IC) is fabricated by using CMOS 0.18 technology. The circuit consists of the RF receiver, RF transmitter and the synthesizer with the on chip oscillator. These proposed chips are fully complies withthe wireless personal area network standard nothing but IEEE 802.15.4 which is for low power consumption. Thevarious specificationsare compared such as noise figure, current consumption, sensitivity, IIP3, percentage EVM. The proposed chips used ultra low 1.8 V power supply with 29mW power consumption for transmitter and 23 mW for reception mode.

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Published

2021-03-27

Issue

2016: ICITER

Section

Articles

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