ANALYSIS OF VEDIC MULTIPLIER

Authors

  • Akshata R. Dept. of Electronics and Communication Gogte Institute of Technology Belagavi, India
  • Prof. V.P. Gejji Dept. of Electronics and Communication Gogte Institute of Technology Belagavi, India
  • Prof. B.R. Pandurangi Dept. of Electronics & Communication Engg., Gogte Institute of Technology Belagavi, India

Keywords:

FPGA, Multiplier, Xilinx.

Abstract

Multipliers are extensively used in FIR filters, Microprocessors, DSP and communication applications. For higher order multiplications, a huge number of adders or compressors are to be used to perform the partial product addition. The need of low power and high speed Multiplier is increasing as the need of high speed processors are increasing. In this paper, a high performance, high throughput and area efficient architecture of a multiplier for the Field Programmable Gate Array (FPGAs) is proposed.

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Published

2021-03-27

Issue

2016: ICCCES

Section

Articles

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How to Cite

Akshata R., Prof. V.P. Gejji, & Prof. B.R. Pandurangi. (2021). ANALYSIS OF VEDIC MULTIPLIER . International Journal of Innovations in Engineering Research and Technology, 1-6. https://repo.ijiert.org/index.php/ijiert/article/view/1058