ADVANCED ENCRYPTION STANDARD WITH LOW AREA & POWER ON FPGA MODULE

Authors

  • Assi.Prof.SarikaN.Wagaj Department of Electronics and Telecommunication,VVPIET Maharashtra India
  • Assi.Prof. Preeti Kadam Department of Electronics and Telecommunication,VVPIET Maharashtra India
  • Assoc. Prof Sajid Shaikh HOD, Department of Electrical& Electronics,VVPIET Maharashtra India

Keywords:

Advanced Encryption Standard (AES), Rijindael Cipher Key (128 bit), FieldProgrammable Gate array (FPGA)

Abstract

Security of the data is most important aspect in communication.In global world security of data is very common parameter.Thereis need for secure transaction in networking, communication, commerce, and secure messaging has moved encryption into the commercial area. Advanced encryption standard (AES) was issued as Federal Information Processing Standards (FIPS) by National Institute of Standards and Technology (NIST) as a successor to data encryption standard (DES) algorithms. The high level of security and the fast hardware and software implementations of the Advanced Encryption Standard (AES) have made it the first choice for many critical applications. For secure data transmissions in wireless military communication and mobile telephony requires encryption with limited area constraints. Therefore, the current workwill befocuses on designing and simulatinglow area AES encryption module and calculate power.

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Published

2021-03-27

Issue

Vol. 3 No. 1 (2016): IJIERT

Section

Articles

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