A Pipelined Fused Processing Unit for DSP Applications
Keywords:
INTRODUCTION, FFT PROCESSOR FOR DSP, FUSED FLOATING POINT TWO- TERM DOT - PRODUCT UNIT, FUSED FLOATING POINT ADD-SUB UNITAbstract
This paper designs a processing element for FFT processor capable of operating on 32-bit double precision floating point numbers. Pipelining is performed on the computational elements of the DSP processor to enhance the throughput. The performance of the Processing unit is increased by using the concept of fused architecture on the sub modules – the dot product unit and the add sub unit. Pipelining increases the speed of the CE of the processor while fused operations claim area optimization. The DSP applications involve FFT Processors that make use of the butterfly operations consisting of multiplications, additions, and subtractions of complex valued data (data is split into real part and the imaginary part). The radix-2 and radix-4 butterflies are designed using fused architecture. The fused FFT butterflies are to be 20 percent speedier and 30 percent smaller in area compared with the conventional method. The processing unit covers almost all the computations necessary for the processor.
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