MODIFIED FREQUENCY SCALING METHOD USED TO 32 BIT X 32 BIT MULTIPRECISION MULTIPLIER

Authors

  • MISS.BHOSALE SHUBHANGI ASHOK Department of Electronics & Telecommunication, VVPIET, Solapur, MS, India
  • PROF.MANTRI D.B. Department of Electronics & Telecommunication, VVPIET, Solapur, MS, India

Keywords:

Computer arithmetic, dynamic voltage scaling, low power design

Abstract

In this paper, we present a multiprecision (MP) reconfigurable multiplier that incorporates variable precision, parallel processing (PP), razor-based dynamic voltage scaling (DVS), and MP operands scheduling are used to providea variety of operating conditions. In Previous paperthe PLLused for the frequency division. If use the PLL for frequency division its hardware complexity increases.To decrease the hardware complexity and also speed is increases aredone by software using some frequency division methods.Thereconfigurable multiplier can either work as independent smaller-precision multipliers or work in parallel to perform higher-precision multiplications. To operate at the proper precision and frequencythe user’s require to configure a dynamic voltage/frequency scaling management unit.

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Published

2021-03-27

Issue

Vol. 4 No. 3 (2017): IJIERT

Section

Articles

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How to Cite

MISS.BHOSALE SHUBHANGI ASHOK, & PROF.MANTRI D.B. (2021). MODIFIED FREQUENCY SCALING METHOD USED TO 32 BIT X 32 BIT MULTIPRECISION MULTIPLIER. International Journal of Innovations in Engineering Research and Technology, 4(3), 1-5. https://repo.ijiert.org/index.php/ijiert/article/view/1315